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| Product Data Sheet SRM-155 SONET/SDH Fiber-Optic Receiver Module with SAW Filter Clock Recovery and Data Retiming Features SONET OC-3 and SDH STM-1 Compatible SAW Filter Clock Recovery and Data Retiming 17 ps Typical Output Jitter PECL Clock and Data Outputs Single +5 Volt Supply CMOS Loss of Signal Flag Operation at 1300 nm and 1550 nm -45 to +85C Operation Wide Dynamic Range Multi-Sourced 20 Pin DIL Footprint The SRM-155 SONET/SDH Fiber-Optic Receiver Module Applications Telecom Receiver Applications Medium and Long Haul SONET/SDH @ 155 Mb/s High Performance Datacom Receiver Applications ATM @ 155 Mb/s Description VTI's SRM-155 is a fully integrated fiber-optic receiver module with SAW filter clock recovery and data retiming. It is ideally suited for SONET OC-3, SDH STM-1 and other 155 Mb/s fiber-optic transmission applications that demand superior performance and stability. SRM-155 SONET/SDH Receiver Module Product Data Sheet Functional Overview This highly integrated module converts a 155 Mb/s fiber-optic NRZ signal to differential PECL recovered clock and retimed data outputs. A CMOS flag alerts the user to a loss of signal condition when the optical input falls below an acceptable level. A single +5 Volt supply provides bias for the module's pin-photodiode, preamplifier, Quantizer, and SAW filter timing recovery circuit. All elements are integrated into fiber-coupled 1.3" X 0.635" 20 pin DIL package. The SRM-155 footprint and pinout are industry common for ease of integration. The optical signal is coupled through a short length of SBJ, Type 2, 62.5 m multimode optical fiber to a hermetic module which encases an InGaAs pinphotodiode and preamplifier. The pin-photodiode converts the optical signal to an electrical current. The signal is then converted to a voltage and amplified by a low noise transimpedance amplifier. Further gain is provided by the quantizer, which also provides a Flag output when the optical signal falls below an acceptable level. The signal is then input to a SAW-filter timing recovery circuit where the the clock signal is recovered, and the data signal is reshaped and retimed. The clock recovery and data retiming function is achieved using a SAW filter technique which is well established and proven through years of application in high performance telecom systems. The clock is extracted from the input NRZ data by first passing it through a frequency doubler to generate sufficient spectral energy at 155 MHz. The SAW filter, a precision narrow band filter, then suppresses jitter by rejecting unwanted frequency spectrum. The extracted clock is then precisely aligned with the data and the signals are reshaped. The output signal is thus free of undesirable jitter and distortion. Unlike phase-looked loop designs, the jitter transfer function of the SRM-155's timing recovery circuit is uniquely stable because it is determined by the shape of the SAW filter's response, which can be precisely controlled. In addition to low output jitter and excellent stability, the SRM-155's timing recovery circuit exhibits fast acquisition time and robust operation No User Connection 17, 18, 19, 20 Vcc 11 Optical Signal InGaAs pin Photodiode GaAs Zt Preamplifier Si Quantizer SAW Timing Recovery Clock 4 Clock 5 Si Decision Circuit Data 7 Data 9 Vd 10 Ground 1,2,3 6,8,13, 15,16 Flag 12 Flag 14 Figure 1. SRM-155 Functional Block Diagram VI 603-598-0070 2 SRM-155 SONET/SDH Receiver Module Product Data Sheet 10 Top View Pin 1 Indicator 11 20 Figure 2. Pin Diagram (Top View) Table 1. Pin Function Pin 4 5 7 9 10 11 12 14 1,2,3,6,8,13,15,16 17,18,19,20 Symbol Clock Clock Data Data VD VCC Flag Flag GND NC PECL Recovered Clock Output. PECL Complementary Recovered Clock Output. PECL Retimed Data Output. PECL Complementary Retimed Data Output. Detector Anode Bias. Ground or apply +5 Volt bias through a series resistor for 1 received optical power monitoring. 5 Volt Supply Voltage. Input Signal Level Status. This CMOS output switches low when the received optical power falls below the status minimum optical power level. Complementary Input Signal Status. CMOS complement of Flag. Ground. No User Connection. Function 1. By connecting pin 10 to a +5 Volt bias through a series resistor (eg. 1 k) received optical power can be monitored as a voltage drop across the resistor. Absolute Maximum Ratings Absolute maximum ratings are provided here as worst case and short duration exposure conditions only. Exposure to conditions more severe than the Absolute Maximum Ratings may result in permanent damage. Exposure to conditions at the Absolute Maximum Ratings for extended periods may also adversely affect device performance or reliability. Functional operation of the device is not implied at these conditions. Table 2. Absolute Maximum Ratings Parameter Storage Temperature Range Supply Voltage pin Detector Bias Lead Soldering Conditions Symbol TS VCC VD Minimum -40 0 0 Maximum 85 +6 +6 250/10 Units C V V C/s VI 603-598-0070 3 SRM-155 SONET/SDH Receiver Module Product Data Sheet Performance Characteristics Table 2. Electrical Performance Parameter Input Signal Rate 1 Symbol fO TO VCC VD ICC 2 Minimum 155.489 -40 4.5 0 Typical 155.520 Maximum 155.551 +85 Units Mb/s C V V mA Operating Temperature Power Supply Voltage pin Detector Bias Voltage (pin10) Power Supply Current Data and Clock Output Levels Low High Clock to Data Alignment 3 4 5.0 0 5.5 +5 300 VOL VOH TCDA TR, TF Duty LOS VCC - 1.95 VCC - 1.03 -100 275 45 375 50 VCC - 1.63 VCC - 0.88 +100 575 55 V V ps ps % Data and Clock Output Rise and Fall Times Output Clock Duty Cycle Received Power Level Flag Decreasing Optical Power Increasing Optical Power Flag Hysteresis Acquisition Time 5 6 -37 -34 Hyst TA JC 17 3 2 dBm dBm dB s ps rms Output Clock Random Jitter 1. Other center frequencies are available in the 124 to 622 MHz frequency range. Please contact t VTI for further details. 2. Measured with a load of RL = 50 to VCC - 2 V. See figures 3 and 4. ECL levels are specified for dc measurement, an additional tolerance of 50 mV should be included for dynamic measurements. 3. Alignment of clock and data outputs (see Figure 5.). 4. Measured at 20% to 80% levels. 5. Time required to achieve valid data and clock outputs with a transition density of at least 50%. +5 V 6. Measured with an input data pseudorandum word 223 - 1. 0.1F +5 V 1H 2.2F 1k 82 10 12 11 9 7 14 82 82 82 2.2F Flag Flag 300 300 SRM-155 4 5 Data Data Clock Clock 124 124 124 124 Figure 3. PECL Interface VI 603-598-0070 4 SRM-155 SONET/SDH Receiver Module Product Data Sheet +5 V 0.1F +5 V 1H 2.2F 1k 10 12 11 9 7 14 2.2F 0.1F 0.1F 0.1F 0.1F Flag Flag 300 300 SRM-155 1,2,3,6,8, 13,15,16 4 5 Data Data Clock Clock 300 300 300 Figure 4. ECL (AC Coupled) Interface TCDA Figure 5. Typical Performance Table 3. Optical Performance Parameter Minimum Average Sensitivity Maximum Optical Input Input Wavelength 1. 1 1 Symbol Sens. PMAX Minimum Typical Maximum -34.0 Units dBm dBm 0 1100 1580 nm For a BER less than 1E-10. Measured using a 223 - 1 pseudorandum word and a 50% average optical duty cycle and a 10 dB Extinction Ratio. VI 603-598-0070 5 SRM-155 SONET/SDH Receiver Module Product Data Sheet Qualification The SRM-155 has been designed to comply with the intent of Bellcore specifications TR-NWT-000468 and TA-TSSY-000983 and will be subject to a complete qualification test plan to demonstrate full compliance. All of the technologies used in the assembly of the module represent standard microelectronics technologies that are used in similar products, and have extensive field reliability data. While all components and technologies used in the optical receiver are backed by qualification data and should present no reliability risk, VTI intends to qualify the fully assembled module with the final design. The qualification plan will entail mechanical and environmental tests along with accelerated life tests. The tests will include those parameters listed below. Table 4. Qualification Plan Parameter Physical Dimensions Mechanical Shock Vibration, variable frequency Lead Solderability Lead Integrity Temperature Cycling High Temperature Aging Low Temperature Storage ESD Destructive Bond Pull Test Method MIL-STD-883, Method 2016 MIL-STD-883, Method2007, Test B MIL-STD-883, Method 2007, Test A MIL-STD-883, Method 2003 MIL-STD-883, Method 2004 -40C/85C, 300 cycles 85C under bias, 3000 hours -40C, 168 hours Method 3015 MIL-STD-883 Sample Size 11 11 11 22 15 11 11 11 3 40 Optical Fiber Characteristics The fiber pigtail is a 30.0 +/-1 inch (measured from the package case to the connector tip) Type 2A multimode fiber with a 62.5 um core. The fiber is encased in a slate colored Strengthened Buffered Jacket (SBJ) cable sheath having a 900 um outer jacket diameter. The minimum fiber bend radius is 1.25 inches. Connectors may be selected to meet the specific requirements of each application. VI 603-598-0070 6 SRM-155 SONET/SDH Receiver Module Product Data Sheet Outline Diagram Figure 5. Outline Diagram Ordering Information Table 5. Part Numbers Fiber-Optic Connector None FC/PC ST SC 1 Model Number SRM-155 SRM-155A SRM-155B SRM-155C VTI Code Number 330001595 330001702 330001710 330001728 1. Other connectors or fiber requirements are available to meet specific application requirements. VI 603-598-0070 7 SRM-155 SONET/SDH Receiver Module Product Data Sheet Notes: For Additional Information Please Contact: Vectron Technologies, Inc. 267 Lowell Road Hudson, NH 03051 Tel: (603) 598-0070 Fax: (603) 598-0075 Vectron Technologies, Inc. reserves the right to make changes to the product(s) and/or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Rev. 0.1, 3/14/97 MDC, /:SRM155F2.SD VI 603-598-0070 8 |
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